1. Technical Field
The present invention relates to a semiconductor integrated circuit and a method for manufacturing thereof, and also relates to a mask employed for a manufacture thereof.
2. Related Art
A typical test pattern utilized for an evaluating a process for a semiconductor integrated circuit will be described. A general view of a layout of a test chip for a general process evaluation is shown in FIG. 7. Maximum values of a width d1 and a vertical width d2 of a test chip are generally defined by employing a maximum field size d3 of a lithographic apparatus. In this case, a maximum field size is presented to be 25 mm. An evaluation pattern is composed of an assembly of evaluation blocks, which are also called sub chip 404. The dimensions of the sub chips are constant in the interior of the testing block. The reason thereof is that this leads to a fixed arrangement and a constant moving distance of measuring probes in a program for measurement, thereby achieving a common use of a program and a sharing of measurement probes.
The pattern for evaluating the interconnect process includes via chains, a pattern for evaluating electro migration (EM), a pattern for measuring a leakage or the like, which are mounted therein. Concerning the via chain, a pattern scaling is generally changed according to the length of the interconnect to be evaluated and the number of vias. A defect density can also be evaluated by utilizing different pattern scaling.
Subsequently, a general process for forming a multiple-layered interconnect will be described, in reference to a process for forming a dual-layered interconnect. Here, FIGS. 8A and 8B, FIGS. 9A and 9B, and FIGS. 10A to 10C are cross-sectional views illustrating the process. FIGS. 11A and 11B, FIGS. 12A and 12B, and FIGS. 13A to 13C are plan views illustrating the process. First of all, an interlayer insulating film 502 composed of a silicon oxide film or the like is formed on a substrate 501 by a chemical vapor deposition (CVD) process or the like (FIG. 8A and FIG. 11A). Elements such as a transistor (not shown) and the like are formed in the substrate 501. In addition to above, a fine region R1 and a rough region R2 in FIG. 8A correspond to the left side and the right side of FIG. 11A, respectively. Such correspondences are also found in FIGS. 8A and 8B, FIGS. 9A and 9B, FIGS. 10A to 10C, FIGS. 11A and 11B, FIGS. 12A and 12B and FIGS. 13A to 13C.
Next, a resist 503 for fluorine (F2) lithography is formed on the interlayer insulating film 502. Then, the resist 503 is patterned with a mask having a pattern of not larger than 0.1 μm by a photolithographic process utilizing F2 wave length (FIG. 8B and FIG. 11B). Further, the pattern of the resist is transferred to the interlayer insulating film 502 by dry etching technology to form trenches 504 for interconnects having linewidth of not larger than 0.1 μm in desired locations. Thereafter, remaining portions of the resist 503 are removed (FIG. 9A and FIG. 12A).
Subsequently, a resist 505 for argon fluoride (ArF) lithography is formed on the interlayer insulating film 502. Then, the resist 505 is patterned with a mask having a pattern of larger than 0.1 μm by a photolithographic process utilizing ArF wave length (FIG. 9B and FIG. 12B). Further, the pattern of the resist is transferred to the interlayer insulating film 502 by dry etching technology to form trenches 506 for interconnects having linewidth of larger than 0.1 μm in desired locations. Thereafter, remaining portions of the resist 505 are removed (FIG. 10A and FIG. 13A).
Then, a conductor film 507 such as copper (Cu) film, aluminum (Al) film and the like is deposited on the entire surface of the interlayer insulating film 502 having the trenches 504 and 506 for interconnects by a CVD process or the like (FIG. 10B, FIG. 13B). Thereafter, the conductor film 507 is polished by a chemical mechanical polishing (CMP) process or the like until the interlayer insulating film 502 is exposed. This results in s formation of an interconnect 508 having a damascene structure in a desired position of the interlayer insulating film 502 (FIG. 10C and FIG. 13C).
FIG. 14 is a plan view, showing an outline of a general logic product. A conventional configuration in general central processing unit (CPU) logic circuits will be described in reference to the diagram. This product has four macro-functions, namely an input-output (I/O) block 701, a random access memory (RAM) block 702, a logic block 703 and a phase locked loop (PLL) block 704.
The I/O block 701 is an area that is composed of only interconnects having the linewidth of not smaller than 1 μm. In such area, there is basically no need for a narrower interconnect. Further, this area serves as determining a limitation on an allowable high-current, and maximum values of the linewidth and the via dimension are determined by such area. An interconnect that connects the circuit blocks in an I/O block is composed of two interconnects, namely an interconnect that is connected to a pad electrode (input interconnect) and an interconnect that is connected to an internal circuit (output interconnect). In conventional structures, such region is provided with a transistor for checking operation mounted therein, and is designed to be provided with a device that has a minimum dimension, which is same as that of the RAM block 702.
The RAM block 702 generally includes a memory device of around 1 MB. A priority is given to a miniaturization for the interconnects in such area over an operating speed. Therefore, this area is an area of highest need for narrower interconnects. Relatively few large interconnects are included in this area, and power supply interconnects and ground interconnects are alternately disposed with a pitch of a memory cell size.
The logic block 703 is a cell, in which higher drive capacity is required, and is also a block, in which power supply interconnects are enhanced. A configuration of this area is basically similar to a configuration of a standard cell of a gate array. The configuration of this area related to the interconnects generally includes enhanced power supply interconnects as compared with that of the RAM, though it is similar to that of RAM. A plurality of connections between macro circuits are generally included, unlikely with the case of the PLL.
Since stable operations of the power supply, the ground and the capacitor element are prioritized in the PLL block 704, the PLL block 704 generally requires second largest linewidth, second only to the I/O region, though the interconnect density therein is lower. The PLL serves as amplifying a signal input from an external transmitter (amplifying a signal to, for example, in 4 times or 5 times of the original), so as to compose clock trees in respective macros. Only two input and output interconnects basically exist in the PLL.
In addition to above, typical prior art documents related to the present invention includes Japanese Laid-Open patent publication No. H6-89839.